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this spec is obsolete spec no: 38-04004 spec title: cy7c276 16k x 16 reprogrammable prom sunset owner: p indira (pci) replaced by: none [+] feedback
16k x 16 reprogrammable prom cy7c276 cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 document #: 38-04004 rev. *c revised september 22, 2006 1cy7c276 features ? 0.8-micron cmos for optimum speed/power ?high speed ? 25-ns access time ? 16-bit-wide words ? three programmable chip selects ? programmable output enable ? 44-pin plcc and 44-pin lcc packages ? 100% reprogrammable in windowed packages ? ttl-compatible i/o ? capable of withstanding greater than 2001v static discharge functional description the cy7c276 is a high-performance 16k-word by 16-bit cmos prom. it is available in a 44-pin plcc and a 44-pin lcc packages, and is 100% reprogrammable in windowed packages. the memory cells utilize proven eprom floating gate technology and word-wide programming algorithms. the cy7c276 allows the user to independently program the polarity of each chip select (cs 2 ? cs 0 ). this provides on-chip decoding of up to eight banks of prom. the polarity of the asynchronous output enable pin (oe) is also programmable. in order to read the cy7c276, all three chip selects must be active and oe must be asserted. the contents of the memory location addressed by the address lines (a 13 ? a 0 ) will become available on the output lines (d 15 ? d 0 ). the data will remain on the outputs until the address changes or the outputs are disabled. 16k x 16 programmable array cs decode d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 lcc/plcc/clcc top view a 13 a 12 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 11 cs 0 cs 1 cs 2 oe 1 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 4443424140 a 13 a 12 a 11 a 10 a 9 v ss v ss a 8 a 7 a 6 a 5 d 12 d 11 d 10 d 9 d 8 v ss v cc d 7 d 6 d 5 d 4 14 a 0 oe a 1 a 2 a 3 a 4 d 0 d 1 d 2 d 3 d d 13 d 15 v v ss v cc cs 2 cs 1 cs 0 v ss ss v cc v ss logic block diagram pin configuration [+] feedback
cy7c276 document #: 38-04004 rev. *c page 2 of 10 maximum ratings [1] (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to+150 c ambient temperature with power applied............................................. ?55 c to+125 c supply voltage to ground potential ................ ?0.5v to+7.0v dc voltage applied to outputs in high z state ................................................ ?0.5v to+7.0v dc input voltage............................................ ?3.0v to +7.0v dc program voltage .................................................... 13.0v uv erasure................................................... 7258 wsec/cm 2 static discharge voltage............................................ >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma selection guide cy7c276-25 cy7c276-30 unit maximum access time 25 30 ns maximum operating current commercial 175 175 ma operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% electrical characteristics [2, 3] parameter description cy7c276-25 cy7c276-30 unit test conditions min. max. v oh output high voltage v cc = min., i oh = ?2.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma (6.0 ma mil) 0.4 v v ih input high level guaranteed input logical hi gh voltage for all inputs 2.0 v cc v v il input low level guaranteed input logical lo w voltage for all inputs ?3.0 0.8 v i ix input leakage current gnd < v in < v cc ?10 +10 a v cd input clamp diode voltage note 2 a i oz output leakage current v cc = max., v ol < v out < v oh , output disabled ?40 +40 a i os output short circuit current v cc = max., v out = 0.0v [4] ?20 ?90 ma i cc power supply current v cc = max., i out = 0.0 ma com?l 175 ma capacitance [2] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 10 pf c out output capacitance 10 pf notes: 1. the voltage on any input or i/o pin cannot exceed the power pin during power-up. 2. see introduction to cmos proms in this data book for general information on testing. 3. see the last page of this specification for group a subgroup testing information. 4. for test purposes, not more than one output at a time should be shorted. short circuit test duration should not exceed 30 sec onds. [+] feedback
cy7c276 document #: 38-04004 rev. *c page 3 of 10 erasure characteristics the recommended dose of ultraviolet light for erasure is a wavelength of 2537 angstroms for a minimum dose (uv intensity multiplied by exposure time) of 25 wsec/cm 2 . for an ultraviolet lamp with a 12 mw/cm 2 power rating the exposure time would be approximately 35 minutes. the cy7c276 needs to be within 1 inch of the lamp during erasure. permanent damage may result if the eprom is exposed to high-intensity uv light for an extended period of time. 7258 wsec/cm 2 is the recommended maximum dosage. wavelengths of light less than 4000 angstroms begin to erase the cy7c276 in the windowed package. for this reason, an opaque label should be placed over the window if the eprom is exposed to sunlight or fl uorescent lighting for extended periods of time. ac test loads and waveforms 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 50 pf including jig and scope 5v output 5 pf including jig and scope (a) normal load (b) high z load < 3ns < 3 n s output 2.0v (1.9v mil) r1 500 ? (658 ? mil) r1 500 ? (658 ? mil) r2 333 ? (403 ? mil) r2 333 ? (403 ? mil) equivalent to: th venin equivalent 200 ? (250 ? mil) switching characteristics over the operating range [2,3] cy7c276-25 cy7c276-30 parameter description min. max. min. max. unit t aa address to output data valid 25 30 ns t csov cs active to output valid 13 15 ns t csoz cs inactive to high z output 13 15 ns t oev oe active to output valid 11 12 ns t oez oe inactive to high z output 11 12 ns [+] feedback
cy7c276 document #: 38-04004 rev. *c page 4 of 10 architecture configuration bits the cy7c276 has four user-programmable options in addition to the reprogrammable data array. for detailed programming information contact your local cypress representative. the programmable options determine the active polarity for the three chip selects (cs 2 ?cs 0 ) and oe. when these control bits are programmed with a 0 the inputs are active low. when these control bits are programmed with a 1 the inputs are active high. programming information programming support is available from cypress as well as from a number of third-party software vendors. for detailed programming information, including a listing of software packages, please see the prom programming information located at the end of this sect ion. programming algorithms can be obtained from any cypress representative. switching waveforms note: 5. cs 2 ? cs 0 , oe assumed active. t oev t csov t csoz read operation timing diagram chip select and output enable timing diagrams addr a addr b data a data b t aa t aa inactive active t oez inactive a 13 ? a 0 cs 2 ? cs 0 oe active high d 15 ? d 0 a 13 ? a 0 d 15 ? d 0 valid valid high z [5] [+] feedback
cy7c276 document #: 38-04004 rev. *c page 5 of 10 control word (4000h) d15 d0 x cs2 cs1 cs0 x x x x x x x x 1 x x oe table 1. control word for architecture configuration control word control option bit programmed level function oe d 0 0 = default 1 = programmed oe active low oe active high cs 0 d 12 0 = default 1 = programmed cs 0 active low cs 0 active high cs 1 d 13 0 = default 1 = programmed cs 1 active low cs 1 active high cs 2 d 14 0 = default 1 = programmed cs 2 active low cs 2 active high bit map programmer address (hex) ram data 0000 data . . . . . . 3fff data 4000 control word table 2. program mode table mode v pp pgm vfy d 0 ? d 15 program inhibit v pp v ihp v ihp high z program enable v pp v ilp v ihp data program verify v pp v ihp v ilp data table 3. configuration mode table mode v pp pgm vfy a 2 d 0 ? d 15 program inhibit v pp v ihp v ihp v pp high z program control word v pp v ilp v ihp v pp control word verify control word v pp v ihp v ilp v pp control word figure 1. programming pinout cy7c276 1 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 65432 44434241 40 a 13 a 12 a 11 a 10 a 9 v ss v ss a 8 a 7 a 6 a 5 d 12 d 11 d 10 d 9 d 8 v ss v cc d 7 d 6 d 5 d 4 14 a 0 oe a 1 a 2 a 3 a 4 d 0 d 1 d 2 d 3 d d 13 d 15 v ss v cc pgm vfy cs 0 v ss v pp v ss v ss [+] feedback
cy7c276 document #: 38-04004 rev. *c page 6 of 10 typical dc and ac characteristics 1.1 1.2 0.9 0.8 0 100 200 300 400 6 1.4 1.2 1.2 1.1 1.0 0.9 4.0 4.5 5.0 5.5 6.0 normalized access time access time (ns) normalized i cc vs. t cka cycle normalized i cc vs. output voltage output voltage (v) supplyvoltage(v) normalized t cka vs. supply voltage 0.7 1.0 1.4 1.2 1.0 0.8 ? 55 125 normalized access time ambient temperature ( c) normalized t cka vs. temperature 30 35 25 15 10 5 0 200 400 600 0 20 output load (pf) t oev change vs. output loading 1.0 0.8 0.6 normalized i (ma) cc normalized i (ma) cc t a =90 c 0.6 25 20 15 10 5 0 200 delta access time (ns) output load (pf) 25 0 800 0.6 0.5 t a = 25 c v cc = 5.5v 500 5.5 5 4.5 4 t a = 25 c f = f max v cc = 4.5v 0.9 400 600 800 1000 t a = 25 c v cc = 4.5v t cka change vs. output loading 0.95 0.90 0.85 ? 55 125 ambient temperature ( c) normalized i cc vs. ambient temperature 25 v cc = 5.6v 1.0 normalized i (ma) cc 1.1 1.1 1.2 1.0 0 0.9 temperature( c) normalized t oev vs. temperature v cc = 4.5v normalized t (ns) oev ? 55 125 25 v cc = 4.5v t a = 25 c 1000 delta t (ns) oev 1.05 [+] feedback
cy7c276 document #: 38-04004 rev. *c page 7 of 10 military specifications group a subgroup testing ordering information speed (ns) ordering code package name package type operating range 25 cy7c276-25hc h67 44-pin windowed leaded chip carrier commercial CY7C276-25JC j67 44-lead plastic leaded chip carrier 30 cy7c276-30jc j67 44-lead plastic leaded chip carrier commercial dc characteristics parameter subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il 1, 2, 3 i ix 1, 2, 3 i oz 1, 2, 3 i cc 1, 2, 3 switching characteristics parameter subgroups t aa 7, 8, 9, 10, 11 t csov 7, 8, 9, 10, 11 t oev 7, 8, 9, 10, 11 [+] feedback
cy7c276 document #: 38-04004 rev. *c page 8 of 10 package diagrams 44-pin windowed leaded chip carrier h67 51-80079-** [+] feedback
cy7c276 document #: 38-04004 rev. *c page 9 of 10 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. all product and company names mentio ned in this document may be the tr ademarks of their respective holders. package diagrams (continued) 44-lead plastic leaded chip carrier j67 51-85003-*a [+] feedback
cy7c276 document #: 38-04004 rev. *c page 10 of 10 document history page document title: cy7c276 16k x 16 reprogrammable prom document number: 38-04004 rev. ecn no. issue date orig. of change description of change ** 113860 03/06/02 dsg change from spec number: 38-00183 to 38-04004 *a 118900 10/09/02 gbi update ordering information *b 122245 12/27/02 rbi add power up requirements to maximum ratings information *c 504720 see ecn pci obsolete device. datasheet to be removed from cypress web and spec. system [+] feedback

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